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With the improvement of IC integration, the requirements for carrier tape production and design are higher and higher

In the past few decades, the packaging form has undergone great changes, from dip → SOIC, TSOP, QFP, PLCC → BGA, PGA → CSP → flip chip, cob or sip.
At the same time, the integration of IC is increasing. The packaged IC is from single chip to dual chip, and then to the current three and four chips. These changes are constantly meeting the requirements of smaller package volume and more functions.
IC changes have higher and higher requirements for carrier tape.
Firstly, the reduction of feature size and the emergence of flipchip cob and sip packaging make the anti-static performance of tape carrier system more and more important;
Secondly, the process of flipchip cob requires that their carrier tape must meet the requirements of the purification workshop for size and high precision.
Of course, the scratch resistance of tape carrier material is also very important.