Because of the influence of COVID-19, we accelerated the shift of semiconductor sealing and testing industry to China. As a capital intensive heavy asset industry

Jiadong rate is the key to enterprise profitability. With the continuous penetration of 5g mobile phones, the accelerated development of automobile electrification and the continuous popularity of the Internet, the demand for high-end and mature chips is strong

The prosperity of the semiconductor industry is high, which indirectly leads to the explosion of orders and full capacity of the later sealing and testing plant

Compared with SOC, system level packaging (SIP) brings the advantages of short R & D cycle, space saving and high integration. SIP technology can not only reduce the repeated packaging of chips, but also reduce the difficulty of layout and wiring

Shorten the R & D cycle. At the same time, the chip stacked 3D SIP package can reduce the use of PCB and save internal space.

In the future, with the rapid development of 5g communication, Internet, artificial intelligence and other technologies, higher requirements are put forward for the size, power consumption and cost of the chip

The progress of packaging technology will become an important way to improve chip performance and a key link to improve electronic system level performance

With the development of advanced packaging and system level packaging (SIP) technology, the equipment and materials of domestic semiconductor industry will usher in broad development prospects.